TECH NEWS – AMD’s new architecture may lag behind Nvidia in raw power, but it could stay competitive through software.

AMD is reportedly working on instruction-level optimizations for its upcoming RDNA 5 GPUs that could, under certain workloads, effectively double performance. RDNA 5 is shaping up as a major overhaul of both architectural and instruction-level features, which is why the first concrete details are being watched so closely.

While it’s still too early to talk about specific SKUs, Coelacanth-Dream – a platform known for closely tracking Linux-related patches – has spotted an intriguing RDNA 5 development aimed at doubling arithmetic throughput via Dual Issue VALU (Vector Arithmetic Logic Unit). In practical terms, that would allow RDNA 5 to “double” effective FP32 capabilities in a range of workloads.

Notably, Dual Issue VALU isn’t new to RDNA 5: AMD already introduced it with RDNA 4 and RDNA 3. The concept is straightforward – two ALU lanes can, in theory, execute two instructions per clock – but recent generations struggled to realize that potential because game-engine compilers didn’t have an efficient way to emit code that consistently fed the dual-issue path. In other words, the hardware capability existed, but RDNA 4/3 couldn’t reliably group and schedule work to exploit it.

With RDNA 5, AMD is said to be introducing FMA (Fused Multiply-Add) in a way that makes it easier for compilers to issue instructions across dual lanes. If compilers can pair more complex ALU operations cleanly and keep those compute lanes busy, the architecture can get much closer to its theoretical peak. For players, the headline implication is higher – and more consistent – frame rates in typical rasterized games.

FMA instructions are also central to neural and AI workloads, complementing AI-driven upscaling (FSR Diamond) and frame generation. If this pans out, RDNA 5’s story may hinge as much on compiler and software-stack maturity as it does on raw silicon.

Source: WCCFTech, Coelacanth-Dream