TECH NEWS – The performance of Tensor Processing Units (TPUs) is important for machine learning and, therefore, artificial intelligence.
ASICs (application-specific integrated circuits) are highly sought after in today’s AI landscape because chips similar to Google’s TPUs are poised to dominate the market at the next level of artificial intelligence applications (i.e., inference), offering superior TCO and performance. Following Google’s introduction of its 7th-generation Ironwood TPUs, both Meta and Anthropic have expressed interest in integrating ASICs into their workloads, furthering the adoption of external TPU applications. However, supply chain constraints pose a significant challenge for Google as it attempts to enter the infrastructure market.
According to China Times, Google’s TPUs fall short of market expectations in terms of chip volume because the company has difficulty sourcing the advanced packaging materials needed for a successful ramp-up from suppliers such as TSMC. Technologies such as CoWoS are among the methods that chip manufacturers have used to achieve significant performance improvements over previous generations. For the TPUv7, Google used an MCM (multi-chip module) design, which allows the company to integrate multiple chips into a single package.
Rather than using a large monolithic chip, the TPUv7 integrates multiple silicon chips into a silicon interposer with microbump arrays that connect the chiplets. This enables scalability and optimizes the internal design of the matrix multipliers and inference structure. Similarly, Ironwood integrates network PHYs and routing logic directly into the package via interposer routing, resulting in extremely low-latency D2D connections. Advanced packaging is an integral part of Google’s TPU technology stack. Therefore, the company must ensure sufficient capacity to support the growth of external applications.
According to a forecast by Fubon Research, Google TPU shipments in 2026 will be lower than those predicted by most analysts, primarily due to the significant CoWoS bottleneck. TSMC’s existing supply chain is tied entirely to Apple and Nvidia products, so bringing in additional customers for advanced packaging would be difficult, even if TSMC increased production capacity significantly. Google would be a relatively new entrant to the supply chain in terms of mass production, so it would certainly be at the end of the line. This does not mean that TPUs will not be introduced; rather, industry bottlenecks make it difficult for Google to offer its custom chips to its broad customer base. One possible solution for Google would be to use companies such as Intel or Amkor for advanced packaging. There are already rumors that the tech giant is exploring EMIB-T solutions.
The AI supply chain is unpredictable when it comes to fulfilling customer orders, so it’s hard to say what Google’s next move will be.
Source: WCCFTech, ChinaTimes
